# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M3
# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M4
# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m5 -resource-pressure=false -noalias=false < %s | FileCheck %s -check-prefixes=ALL,M5

st3	{v0.s, v1.s, v2.s}[0], [sp]
st3	{v0.2s, v1.2s, v2.2s}, [sp]

st3	{v0.d, v1.d, v2.d}[0], [sp]
st3	{v0.2d, v1.2d, v2.2d}, [sp]

st3	{v0.s, v1.s, v2.s}[0], [sp], #12
st3	{v0.2s, v1.2s, v2.2s}, [sp], #24

st3	{v0.d, v1.d, v2.d}[0], [sp], #24
st3	{v0.2d, v1.2d, v2.2d}, [sp], #48

st3	{v0.s, v1.s, v2.s}[0], [sp], x0
st3	{v0.2s, v1.2s, v2.2s}, [sp], x0

st3	{v0.d, v1.d, v2.d}[0], [sp], x0
st3	{v0.2d, v1.2d, v2.2d}, [sp], x0

# ALL:      Iterations:        100
# ALL-NEXT: Instructions:      1200

# M3-NEXT:  Total Cycles:      18003
# M3-NEXT:  Total uOps:        8400

# M4-NEXT:  Total Cycles:      3903
# M4-NEXT:  Total uOps:        5000

# M5-NEXT:  Total Cycles:      3603
# M5-NEXT:  Total uOps:        4400

# ALL:      Dispatch Width:    6

# M3-NEXT:  uOps Per Cycle:    0.47
# M3-NEXT:  IPC:               0.07
# M3-NEXT:  Block RThroughput: 72.0

# M4-NEXT:  uOps Per Cycle:    1.28
# M4-NEXT:  IPC:               0.31
# M4-NEXT:  Block RThroughput: 21.0

# M5-NEXT:  uOps Per Cycle:    1.22
# M5-NEXT:  IPC:               0.33
# M5-NEXT:  Block RThroughput: 10.5

# ALL:      Instruction Info:
# ALL-NEXT: [1]: #uOps
# ALL-NEXT: [2]: Latency
# ALL-NEXT: [3]: RThroughput
# ALL-NEXT: [4]: MayLoad
# ALL-NEXT: [5]: MayStore
# ALL-NEXT: [6]: HasSideEffects (U)

# ALL:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:

# M3-NEXT:   5      14    4.50           *            st3	{ v0.s, v1.s, v2.s }[0], [sp]
# M3-NEXT:   7      15    6.00           *            st3	{ v0.2s, v1.2s, v2.2s }, [sp]
# M3-NEXT:   7      15    6.00           *            st3	{ v0.d, v1.d, v2.d }[0], [sp]
# M3-NEXT:   9      16    7.50           *            st3	{ v0.2d, v1.2d, v2.2d }, [sp]
# M3-NEXT:   5      14    4.50           *            st3	{ v0.s, v1.s, v2.s }[0], [sp], #12
# M3-NEXT:   7      15    6.00           *            st3	{ v0.2s, v1.2s, v2.2s }, [sp], #24
# M3-NEXT:   7      15    6.00           *            st3	{ v0.d, v1.d, v2.d }[0], [sp], #24
# M3-NEXT:   9      16    7.50           *            st3	{ v0.2d, v1.2d, v2.2d }, [sp], #48
# M3-NEXT:   5      14    4.50           *            st3	{ v0.s, v1.s, v2.s }[0], [sp], x0
# M3-NEXT:   7      15    6.00           *            st3	{ v0.2s, v1.2s, v2.2s }, [sp], x0
# M3-NEXT:   7      15    6.00           *            st3	{ v0.d, v1.d, v2.d }[0], [sp], x0
# M3-NEXT:   9      16    7.50           *            st3	{ v0.2d, v1.2d, v2.2d }, [sp], x0

# M4-NEXT:   2      2     1.00           *            st3	{ v0.s, v1.s, v2.s }[0], [sp]
# M4-NEXT:   4      4     2.00           *            st3	{ v0.2s, v1.2s, v2.2s }, [sp]
# M4-NEXT:   2      2     1.00           *            st3	{ v0.d, v1.d, v2.d }[0], [sp]
# M4-NEXT:   6      5     3.00           *            st3	{ v0.2d, v1.2d, v2.2d }, [sp]
# M4-NEXT:   3      2     1.00           *            st3	{ v0.s, v1.s, v2.s }[0], [sp], #12
# M4-NEXT:   5      4     2.00           *            st3	{ v0.2s, v1.2s, v2.2s }, [sp], #24
# M4-NEXT:   3      2     1.00           *            st3	{ v0.d, v1.d, v2.d }[0], [sp], #24
# M4-NEXT:   7      5     3.00           *            st3	{ v0.2d, v1.2d, v2.2d }, [sp], #48
# M4-NEXT:   3      2     1.00           *            st3	{ v0.s, v1.s, v2.s }[0], [sp], x0
# M4-NEXT:   5      4     2.00           *            st3	{ v0.2s, v1.2s, v2.2s }, [sp], x0
# M4-NEXT:   3      2     1.00           *            st3	{ v0.d, v1.d, v2.d }[0], [sp], x0
# M4-NEXT:   7      5     3.00           *            st3	{ v0.2d, v1.2d, v2.2d }, [sp], x0

# M5-NEXT:   2      2     1.00           *            st3	{ v0.s, v1.s, v2.s }[0], [sp]
# M5-NEXT:   3      4     1.00           *            st3	{ v0.2s, v1.2s, v2.2s }, [sp]
# M5-NEXT:   2      2     1.00           *            st3	{ v0.d, v1.d, v2.d }[0], [sp]
# M5-NEXT:   5      4     1.50           *            st3	{ v0.2d, v1.2d, v2.2d }, [sp]
# M5-NEXT:   3      2     1.00           *            st3	{ v0.s, v1.s, v2.s }[0], [sp], #12
# M5-NEXT:   4      4     1.00           *            st3	{ v0.2s, v1.2s, v2.2s }, [sp], #24
# M5-NEXT:   3      2     1.00           *            st3	{ v0.d, v1.d, v2.d }[0], [sp], #24
# M5-NEXT:   6      4     1.50           *            st3	{ v0.2d, v1.2d, v2.2d }, [sp], #48
# M5-NEXT:   3      2     1.00           *            st3	{ v0.s, v1.s, v2.s }[0], [sp], x0
# M5-NEXT:   4      4     1.00           *            st3	{ v0.2s, v1.2s, v2.2s }, [sp], x0
# M5-NEXT:   3      2     1.00           *            st3	{ v0.d, v1.d, v2.d }[0], [sp], x0
# M5-NEXT:   6      4     1.50           *            st3	{ v0.2d, v1.2d, v2.2d }, [sp], x0
